A complete abrasive‐free process for fabricating copper damascene interconnection has been developed. The process is a combination of newly developed abrasive‐free polishing (AFP) of Cu and dry etching of a barrier metal layer. A new aqueous chemical polishing solution and a polyurethane polishing pad produce complete stop‐on‐barrier characteristics of Cu polishing. The AFP provides a very clean, scratch‐free, anticorrosive polished surface, and the total depth of erosion and dishing is reduced to less than one fifth of that produced by conventional slurries, even after 100% overpolishing. The barrier metal is successfully dry etched by using SF6 gas at a high selectivity ratio (more than 10) of barrier metal to SiO2 . It was found that the developed AFP significantly reduces both Cu line resistance and its deviation. Moreover, AFP can also contribute to cost reduction of chemical mechanical polishing and help solve environmental problems related to waste slurries. © 2000 The Electrochemical Society. All rights reserved.
The use of highly packed multilevel interconnections with low resistance and low parasitic capacitance has attracted much attention as a method for increasing operating speed of ultralarge scale integrated circuits (ULSIs). 1 Copper (Cu) metallization has been intensively studied for increasing current density as well as reducing the resistance of interconnections and is going to be put to practical use. 2,3 The damascene process is expected to be very promising for producing fine Cu lines, 4 and the key to establishing this process is chemical mechanical polishing (CMP) of Cu and barrier metals. Slurries for Cu CMP usually contain an oxidizer, abrasive powder, etching chemicals of Cu or Cu oxide, and an inhibitor when necessary. 5,6 Kaufman et al. proposed a mechanism of tungsten CMP, a mechanism thought to be common to many kinds of metals, i.e., oxidation of the metal surface, removal of the oxide on protruding areas by abrasive particles in the slurry, and reoxidation of the exposed metal surface. 7 In order to provide damascene metal lines of high accuracy and at a high yield, the optimization of chemical characteristics of slurries and the CMP conditions have been investigated for achieving a large removal rate while suppressing dishing and erosion. 8 The Cu films, however, are very quick to corrode or be etched, especially in a wet-chemical environment. Two types of corrosion are known to occur during Cu CMP. One is chemical corrosion due to the chemical reaction of Cu with chemicals in the slurry, and the other is galvanic corrosion that occurs when two electrochemically different metals are electrically connected and exposed to the same electrolyte. Since these types of corrosion would result in pattern defects and loss of metal thickness (resistance increase), the chemicals of the Cu CMP slurry must be chosen carefully.This paper reports on the investigation of corrosion induced by Cu CMP slurries and describes a new mode of corrosion called pattern-specific corrosion. This paper also clarifies that this corrosion is due to photoillumination during interconnection fabrication; 9 thus, it may also be called photocorrosion. 10 Experimental CMP conditions and slurries.-A dead-weight-type CMP apparatus with an 18 in. diam platen was used with a grid-grooved, foamed polyurethane polishing pad (IC1000, Rodel Co.). The linear velocity of the wafer center to the polishing pad was varied from 25 to 50 m/min, and the down forces were varied from 140 to 210 g/cm 2 (13.7-21.6 kPa). Two kinds of alumina-based slurries were prepared. Slurry A is a mixture of hydrogen peroxide solution (H 2 O 2 , 30 wt % in water) and a commercially available, alumina abrasive suspension (QCTT1010, Rodel). The hydrogen exponent pH of the suspension is about 4.5. Though the suspension is an old one, it was chosen because it has been widely used as the standard suspension commercially available. The recommended mixing ratio of QCTT1010 to H 2 O 2 is 7:3 (volume ratio). Slurry B is a mixture of H 2 O 2 and an experimental alumina abrasiv...
A model for stress-induced metal notching and voiding in very large-scale-integrated Al-Si (1%) metallization J.This paper presents a study on grain boundary fracture failures found in AI-Si interconnects during aging tests without electric current flow. Failure rate analysis and microscopic observation by transmission electron microscopy and scanning electron microscopy indicate that failures are caused by slitlike voids formed at grain boundaries during the relaxation process in AI-Si conductors stressed by temperature cycling under the volume constraint of passivation films. Conductors are seen to fail in two modes; an open mode at bamboolike grain boundaries and a high-resistance mode at grain boundaries having large silicon precipitates.
Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH3-plamsa treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime ( G~) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CUN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Futhermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects, such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the Si02 surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB .
A 0.2-pm bipolar-CMOS process technology on a bonded SO1 wafer was developed for ultra-high-speed applications. This process was used to fabricate a new-cache memory chip consisting of 9-Mb 0.6-11s SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-pm bipolar-CMOS process features a 6-pm2-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SO1 wafer with deep and shallow trench isolations was used to maximize the BJT performance.
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