State-of-the-art transistors achieve their improved performance through strain engineering. The somewhat unusual uniaxial ͓110͔ strain is of particular importance as it provides a significant mobility increase for electrons. Empirical tight binding has shown tremendous benefits in modeling realistically large structures including standard strain conditions, but often fails to predict the correct uniaxial ͓110͔ strain behavior because most treatments neglect the same-atom different-orbital matrix elements induced by this strain. Two separate mechanisms are responsible for these conditions: Löwdin orbital changes and displacement of nearest-neighbor potentials. We present a model which separately includes both mechanisms via parameters whose range of validity can be independently determined. Using this method we optimize a set of strain parameters for Si. The combination of both effects is able to reproduce the Si X z-valley transverse mass splitting under uniaxial ͓110͔ strain. We then use this model to calculate the drain current of a strained double-gate, ultrathin-body metaloxide-semiconductor field-effect transistor, finding experimentally plausible results.

An enhanced valence force field model for zincblende crystals is developed to provide a unified description of the isothermal static and dynamical lattice properties of gallium arsenide. The expression for the lattice energy includes a second-nearest-neighbor coplanar interaction term, the Coulomb interaction between partially charged ions, and anharmonicity corrections. General relations are derived between the microscopic force constants and the macroscopic elastic constants in zincblende crystals. Applying the model to gallium arsenide, parameter sets are presented that yield quantitative agreement with experimental results for the phonon dispersion, elastic constants, sound velocities, and Grüneisen mode parameters.

No abstract

No abstract

A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness (TOX) for each gate stack, including SiO2 interface layer and one high-k material. For the same EOT, Al2O3 (k=9) over 3Å SiO2 provides the best performance, while for HfO2 (k=20) and La2O3 (k=30), SiO2 thicknesses should be 5Å and 7Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.