The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is ‘transferred’ to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.

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Block copolymer (BCP) microphase separation at surfaces might enable the generation of substrate features in a scalable, manufacturable, bottom-up fashion provided that pattern structure, orientation, alignment can be strictly controlled. A further requirement is that self-assembly takes place within periods of the order of minutes so that continuous manufacturingprocesses do not require lengthy pretreatments and sample storageleading to contamination and large facility costs. We report here microwave-assisted solvothermal (in toluene environments) self-assembly and directed self-assembly of a very low molecular weight cylinder-forming polystyrene-block-polydimethylsiloxane (PS-b-PDMS) BCP on planar and patterned silicon nitride (Si3N4) substrates. Good pattern ordering was achieved in the order of minutes. Factors affecting BCP self-assembly, notably anneal time and temperature were studied and seen to have significant effects. Graphoepitaxy to direct self-assembly in the BCP yielded promising results producing BCP patterns with long-range translational alignment commensurate with the pitch period of the topographic patterns. This rapid BCP ordering method is consistent with the standard thermal/solvent anneal processes.

A novel, simple and in situ hard mask technology that can be used to develop high aspect ratio silicon nanopillar and nanowire features on a substrate surface is demonstrated. The technique combines a block copolymer inclusion method that generates nanodot arrays on substrate and an inductively coupled plasma (ICP) etch processing step to fabricate Si nanopillar and nanowire arrays. Iron oxide was found to be an excellent resistant mask over silicon under the selected etching conditions. Features of a very high aspect ratio can be created by this method. The nanopillars have uniform diameter and smooth sidewalls throughout their entire length. The diameter (15-27 nm) and length of the nanopillars can be tuned easily. Different spectroscopic and microscopic techniques were used to examine the morphology and size, surface composition and crystallinity of the resultant patterns. The methodology developed may have important technological applications and provide an inexpensive manufacturing route to nanodimensioned topographical patterns. The high aspect ratio of the features may have importance in the area of photonics and the photoluminescence properties are found to be similar to those of surface-oxidized silicon nanocrystals and porous silicon.