This paper proposes a novel system-level power estimation methodology for electronic designs consisting of intellectual property (IP) components. Our methodology relies on analytical output and power macromodels of the IP blocks to estimate system dissipation without petforniing any simulation. We derive upper bounds on the estimation error of our methodology and demonstrate the relation of this error to the sensitivities of the macromodeling functions. For circuits without feedback, we give a siijj'icient condition for the worst-case power estimation error to increase only linearly with the length of the IP cascades. We also give a tighter siificient condition that ensiires error boundedness in IP systems of any topology. Experiments with signal processing and data encryption systems validate the accuracy and eflciency of our approach. For designs of up to 576 IP blocks, power estimates are obtained within 0.2 seconds. In comparison with switch-level simulation results, the average error of our power estimates is 7.3%.