An increasing corpus of research focuses on inferring contexts solely through analysis of changes in surrounding wireless signals without the subject carrying a device (devicefree). This paper takes device-free recognition a step further: We present WiDisc, a novel device-free RF system for distinguishing three subject classes (e.g. tall, medium, small). WiDisc models the problem as fingerprinting-based classification. To alleviate the significant location-based training overhead per subject class which is usually required, WiDisc employs 3D subject class model construction and electromagnetic simulations to generate the fingerprints with no manual training overhead. WiDisc further estimates the most relevant RF links to maximize recognition performance. Our lab evaluation with only four transceivers and three subject classes shows that the link selection module can accurately predict the two most important links, falling short only 5% of the achievable accuracy. In addition, WiDisc achieves a classification accuracy of 67% with zero training overhead vs 76% with traditional fingerprinting. Discrimination works well for the medium and tall subjects but confusions for the small subject are frequent, indicating potential for further research. Still, the results highlight WiDiscs ability to trade off accuracy and training overhead and opens the door for new device-free applications such as parental control or personalized gesture recognition.
Traditional design techniques for FPGAs are based on using hardware description languages, with functional and postplace-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations.
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