is an order magnitude larger than previously thought, yet near the low end of known solidsolid interfaces. Our study also reveals unexpected insight into non-uniformities of the MoS2 transistors (small bilayer regions), which do not cause significant self-heating, suggesting that such semiconductors are less sensitive to inhomogeneity than expected. These results provide key insights into energy dissipation of 2D semiconductors and pave the way for the future design of energy-efficient 2D electronics. Keywords: Energy dissipation, 2D semiconductors, thermal boundary conductance, Raman thermometry, MoS2 2The performance of nanoelectronics is most often constrained by thermal challenges, 1, 2 memory bottlenecks, 3 and nanoscale contacts. 4 The former have become particular acute, with high integration densities leading to high power density, and numerous interfaces (e.g. between silicon, copper, SiO2) leading to high thermal resistance. New applications and new form-factors call for dense vertical integration into multi-layer "high-rise" processors for high-performance computing, 3 or integration with poor thermal substrates like flexible plastics (of thermal conductivity 5xlower than SiO2 and nearly 500x lower than silicon) for wearable computing. 5 These are the two most likely platforms for incorporating 2D semiconductors into electronics, yet very little is known about fundamental limits or practical implications of energy dissipation in these contexts.At its most basic level, energy dissipation begins in the ultra-thin transistor channel and is immediately limited by the insulating regions and thermal resistance with the interfaces surrounding it. Herbert Kroemer's observation 6 that "the interface is the device" is remarkably aptfor 2D semiconductors such as monolayer MoS2. These have no bulk, and are thus strongly limited by their interfaces. For instance, even some of the best electrical contacts known today add >50% parasitic resistance to MoS2 transistors when these are scaled to sub-100 nm dimensions. Similarly, thermal interfaces may be expected to limit energy dissipation from 2D electronics, and their understanding is essential. Nevertheless, a key challenge is the need to differentiate heating of the sub-nanometer thin 2D material from its environment. Here, Raman spectroscopy holds a unique advantage, 8, 9 as the temperature of even a monolayer semiconductor can be distinguished from the material directly under (or above) it, if the Raman signatures are distinct. 10Figure 1a shows our typical device structure and measurement setup. We utilize high-qual- Minor, randomly distributed non-uniformities in the temperature seen in Figure 2 are within the uncertainty of the measurement and are also visible in the reference map taken at VDS = 0 (on a hot stage), for which the temperature is known to be uniform, as shown in Supporting Information Figure S4. The uniform self-heating of transistors from CVD-grown MoS2 suggests that any change in energy dissipation around the 2L spots or other non-uniformit...

Despite much interest in applications of two-dimensional (2D) fabrics such as MoS, to date most studies have focused on single or few devices. Here we examine the variability of hundreds of transistors from monolayer MoS synthesized by chemical vapor deposition. Ultraclean fabrication yields low surface roughness of ∼3 Å and surprisingly low variability of key device parameters, considering the atomically thin nature of the material. Threshold voltage variation and very low hysteresis suggest variations in charge density and traps as low as ∼10 cm. Three extraction methods (field-effect, Y-function, and effective mobility) independently reveal mobility from 30 to 45 cm/V/s (10th to 90th percentile; highest value ∼48 cm/V/s) across areas >1 cm. Electrical properties are remarkably immune to the presence of bilayer regions, which cause only small conduction band offsets (∼55 meV) measured by scanning Kelvin probe microscopy, an order of magnitude lower than energy variations in Si films of comparable thickness. Data are also used as inputs to Monte Carlo circuit simulations to understand the effects of material variability on circuit variation. These advances address key missing steps required to scale 2D semiconductors into functional systems.

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We demonstrate monolayer MoS2 grown by chemical vapor deposition (CVD) with transport properties comparable to those of the best exfoliated devices over a wide range of carrier densities (up to ~10 13 cm -2 ) and temperatures (80-500 K). Transfer length measurements (TLM) decouple the intrinsic material mobility from the contact resistance, at practical carrier densities (>10 12 cm -2 ). We demonstrate the highest current density reported to date (~270 μA/μm or 44 MA/cm 2 ) at 300 K for an 80 nm device from CVD-grown monolayer MoS2. Using simulations, we discuss what improvements of monolayer MoS2 are still required to meet technology roadmap requirements for low power (LP) and high performance (HP) applications. Such results are an important step towards large-area electronics based on monolayer semiconductors.

Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with conventional semiconductor processing or introduce time-dependent, hysteretic behavior. Here we show that low temperature (< 200°C) sub-stoichiometric AlO x provides a stable n-doping layer for monolayer MoS 2 , compatible with circuit integration. This approach achieves carrier densities >2×10 13 cm -2 , sheet resistance as low as ~7 kΩ/□, and good contact resistance ~480 Ω⋅μm in transistors from monolayer MoS 2 grown by chemical vapor deposition. We also reach record current density of nearly 700 μA/μm (>110 MA/cm 2 ) in this three-atom-thick semiconductor while preserving transistor on/off current ratio > 10 6 . The maximum current is ultimately limited by self-heating and could exceed 1 mA/μm with better device heat sinking. With their 0.1 nA/μm off-current, such doped MoS 2 devices approach several low-power transistor metrics required by the international technology roadmap.