Kedong Zhang scite author profile

Kedong Zhang

133Publications

1,372Citation Statements Received

894Citation Statements Given

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Affiliations

Soochow University, Intel (United States)

Publications

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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

Natarajan¹,

Agostinelli²,

Akbar³

et al. 2014

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Cutting performance and wear mechanism of nanoscale and microscale textured Al2O3/TiC ceramic tools in dry cutting of hardened steel

Xing

Deng

Zhao

et al. 2014

International Journal of Refractory Metals and Hard Materials

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High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

Packan

Akbar

Armstrong

et al. 2009

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A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Auth

Balakrishnan

Bost

et al.

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Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

Mistry

Armstrong

Auth

et al. 2004

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Effect of microscale texture on cutting performance of WC/Co-based TiAlN coated tools under different lubrication conditions

Zhang

Deng

Xing

et al. 2015

Applied Surface Science

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Study on the adhesion and tribological behavior of PVD TiAlN coatings with a multi-scale textured substrate surface

Zhang

Deng

Guo

et al. 2018

International Journal of Refractory Metals and Hard Materials

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Improving dry machining performance of TiAlN hard-coated tools through combined technology of femtosecond laser-textures and WS2 soft-coatings

Zhang

Deng

Ding

et al. 2017

Journal of Manufacturing Processes

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12 3 4 5

Kedong Zhang

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

Cutting performance and wear mechanism of nanoscale and microscale textured Al2O3/TiC ceramic tools in dry cutting of hardened steel

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

Effect of microscale texture on cutting performance of WC/Co-based TiAlN coated tools under different lubrication conditions

Study on the adhesion and tribological behavior of PVD TiAlN coatings with a multi-scale textured substrate surface

Improving dry machining performance of TiAlN hard-coated tools through combined technology of femtosecond laser-textures and WS2 soft-coatings

Kedong Zhang

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size

Cutting performance and wear mechanism of nanoscale and microscale textured Al2O3/TiC ceramic tools in dry cutting of hardened steel

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

Effect of microscale texture on cutting performance of WC/Co-based TiAlN coated tools under different lubrication conditions

Study on the adhesion and tribological behavior of PVD TiAlN coatings with a multi-scale textured substrate surface

Improving dry machining performance of TiAlN hard-coated tools through combined technology of femtosecond laser-textures and WS2 soft-coatings

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size