We propose a scheme for transient -

We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for transient-fault detection, called Simultaneously and Redundantly Threaded (SRT) processors. SRT replicates an application into two communicating threads, one executing ahead of the other. The trailing thread repeats the computation performed by the leading thread, and the values produced by the two threads are compared. In SRT, a leading instruction may commit before the check for faults occurs, relying on the trailing thread to trigger detection. In contrast, SRTR must not allow any leading instruction to commit before checking occurs, since a faulty instruction cannot be undone once the instruction commits. To avoid stalling leading instructions at commit while waiting for their trailing counterparts, SRTR exploits the time between the completion and commit of leading instructions. SRTR compares the leading and trailing values as soon as the trailing instruction completes, typically before the leading instruction reaches the commit point. To avoid increasing the bandwidth demand on the register file for checking register values, SRTR uses the register value queue (RVQ) to hold register values for checking. To reduce the bandwidth pressure on the RVQ itself, SRTR employs dependence-based checking elision (DBCE). By reasoning that faults propagate through dependent instructions, DBCE exploits register (true) dependence chains so that only the last instruction in a chain uses the RVQ, and has the leading and trailing values checked. SRTR performs within 1% and 7% of SRT for SPEC95 integer and floating-point programs, respectively. While SRTR without DBCE incurs about 18% performance loss when the number of RVQ ports is reduced from four (which is performance-equivalent to an unlimited number) to two ports, with DBCE, a two-ported RVQ performs within 2% of a four-ported RVQ.

Matrix computation such as matrix addition, subtraction, multiplication and inversion are frequently used in various fields for research and engineering application. It is a very important tool for image processing, speech recognition and signal processing for spectral analysis and beam forming … etc... As the area of computer application has broadened, the quantity of data to be operated has greatly increased. With a serial machine as we have now in the 2-D computer system it is becoming too much time consuming in matrix computation to meet the applications. The speed of data processing can be increased or improved by using the 3-D parallel processor, a 3-D IC hardware machine. With the advancement of the TSV (Through Silicon Via), wafer to wafer interconnection and stacking technologies in 3-D IC manufacturing, it has become relatively easy and low cost to produce a 3-D parallel processor to meet the requirement for advance research and engineering. What will be the different between the 2-D and 3-D processor is that the processing algorithm and the circuit design architecture. A 3-D processor can be designed to execute the data signal paralleling while the conventional 2-D is sequentially. Therefore, the power of the 3-D data processing could be much greater than that of the 2-D version. This paper will describe how this 3-D IC design architecture for handling great number of data processing for matrix inversion as an example in comparing with the current 2-D machine in processing power and execution time.

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Performing electrical test is the most challenge process in the 3D-IC device fabrication and manufacturing. There have been many papers published and presented for 3D-IC device testing technology such as 3D-IC design for test, test for less in the 3D-IC manufacturing etc... Most of them are circuit design related techniques. In this paper we will discuss a different point of view in the device packaging technologies that may affect the cost of testing.The main technologies for integrating and fabricating the 3D-IC device and system are (1) Through Silicon Via (TSV) technology for vertical communication;(2) interconnecting technology to accomplish the up and down signal flow between wafer layers and (3) stacking technology to complete the final assembly of the 3D-IC device and system. One very important step in the integration and manufacturing process is the testing and evaluating of the 3D-IC stacked system. This paper will dedicate to the issue of choosing the right interconnecting technology for cost effective consideration by introducing the Micro Bridge Technology. With the right choice of interconnecting technology, we will be benefited from the reduction of the 3D-IC system integration and testing through both cost and complexity. CURRENT 3D-IC INTERCONNECTING TECHNOLOGIESA lot of researches have been dedicated to the 3D-IC interconnecting technology. Among them the 3 kinds of interconnection technology are the most popular ones. They are (1) Interposer (with silicon or glass or membrane substrate) (2) Microbump and (3) Micro-Bridge. The advantages of using the Microbridge as the interconnection are (1) to compensate for warping of the wafer surface introduced during the circuit fabrication processing and (2) the stack can be disassembled and the individual wafers or silicon substrates can be demounted for re-test and/or replacement.