In light of ignoring the effect of backlash on mesh stiffness in existing gear dynamic theory, a precise profile equation was established based on the generating processing principle. An improved potential energy method was proposed to calculate the mesh stiffness. The calculation result showed that when compared with the case of ignoring backlash, the mesh stiffness with backlash had an obvious decrease in a mesh cycle and the rate of decline had a trend of decreasing first and then increasing, so a stiffness coefficient was introduced to observe the effect of backlash. The Fourier series expansion was employed to fit the mesh stiffness rather than time-varying mesh stiffness, and the stiffness coefficient was fitted with the same method. The time-varying mesh stiffness was presented in terms of the piecewise function. The single degree of freedom model was employed, and the fourth order Runge–Kutta method was utilized to investigate the effect of backlash on the nonlinear dynamic characteristics with reference to the time history chart, phase diagram, Poincare map, and Fast Fourier Transformation (FFT) spectrogram. The numerical results revealed that the gear system primarily performs a non-harmonic-single-periodic motion. The partially enlarged views indicate that the system also exhibits small-amplitude and low-frequency motion. For different cases of backlash, the low-frequency motion sometimes shows excellent periodicity and stability and sometimes shows chaos. It is of practical guiding significance to know the mechanisms of some unusual noises as well as the design and manufacture of gear backlash.
Urban road system is the basic bone of urban transportation and one of the most important factors that influent and controls the urban configuration. In this paper, an approach of modeling, analyzing and optimizing urban road system is described based on complex network theory and GIS technology. The urban road system is studied on three focuses: building the urban road network, modeling the computational procedures based on urban road networks and analyzing the urban road system of Changzhou City as the study case. The conclusion is that the urban road network is a scale-free network with small-world characteristic, and there is still space for development of the whole network as a small-world network, also the key road crosses should be kept expedite.
A high performance RFCMOS SoC GPS navigation solution is introduced. It supports various location and navigation applications, including autonomous GPS, SBAS, DGPS (RTCM), and AGPS in L1-band at 1575.42MHz. A wide range of reference frequencies are supported to comply with other handheld specifications. The base-band architecture is optimized for the correlation efficiency and the power consumption of one single correlating operation. Hence this SoC receiver achieves the industry's highest levels of sensitivity, accuracy, and Time-to-First-Fix (TTFF) with the lowest power consumption. PMIC is also integrated in the SoC, no external LDO and power switching circuit is needed for all voltage domains, including RTC.As mobile devices with GPS/navigation feature and location-based-service (LBS) become more and more popular, single chip GPS SoC receiver becomes the main trend [1][2][3]. A low power SiGe BiCMOS GPS radio for cell phones is introduced in [4]. This chip achieves low power, high performance and is highly integration with minimum external components compared to [1][2][3][4]. The block diagram is shown in Fig. 14.3.1. The RF frond-end, GPS engine, PMIC, ARM processor and peripheral controllers are all integrated in a single SoC.For the RF part, this chip delivers a total receiver noise figure of 3.2 dB with integrated LNA. With on-chip image-rejection mixer, the specification of an external SAW filter is alleviated, and with embeded automatic center frequency calibration band pass filter, an external filter is not required. To achieve the RF performance with CMOS SoC, Native NTN is put between RF and digital baseband to create a high resistance substrate. For RF sensitive blocks, P+ guard ring is used, and for RF noisy blocks, D-NWELL guard ring is chosen. The floorplan is also considered and RF macro is put at the upper left corner to minimize the noise from two sides only. Low frequency RTC and memories are put beside the RF part as an isolation component. Ground balls for RF are independent, and sensitive RF pins are surrounded by the ground for separation. In order to minimize the interference to RF in-band, the harmonics of PLL output frequencies are analyzed to make sure no high-order harmonics may drop in the range. A wide range of reference frequencies can be supported, and a low-power integer-N mode is provided for some commonly used frequencies, such as 16.368 and 26MHz. Up to 25% of RF current consumption can be saved with integer-N mode.Various power schemes are supported with internal PMIC integration. No external LDOs are needed and a single power supply ranging from 3.3 to 4.2V is enough for all power requirements. A low quiescent-current LDO is integrated in RTC domain. It is also the first GPS SoC that integrates a switching mode power supply (SMPS) to support energy-lossless voltage transfer. Its interference to RF part is suppressed by carefully controlling the voltage/current slew rate and the size of power MOS pre-driving circuit. The leakage current of the whole RTC domain, including LDO...
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