JapanFor monolithic integration of an analog/digital compatible circuit, a high-voltage shallow junction process with a complementary dielectric isolation technique has been developed. Both high-voltage and high-frequency requirements can be simultaneously, and easily met with this technique.In this process, complementary high-voltage transistors (BVbco>350V) are fabricated by employing shallow junctions (X <2pm) which are used in common with high-frequency low-voltage devices. To realize a high breakdown voltage with shallow junctions, a combination of a field-plate structure, optimized by computer simulation, and semi-insulating film passivation is adopted. PNP as well as NPN transistors are formed in a vertical structure using a newly developed self-aligning complementary dielectric isolation technique. The transistors made by this 350V process have highfrequency characteristics {fT(NPN)=450MHz; f (PNP)=2OOMHZ}, and an excellent hFE complementarity between NPN and PNP transistors. One of the most important applications of this process is the integration of subscriber line interface circuits for a digital local switching system. An L S I with battery feed, supervision and 2wire-4wire hybrid functions has been successfully fabricated with this process. jb T Fig. 1Table 1 Fig. 2Fig. 3Fig. 4 SUPPLEMENT A schematic cross-sectional view of the high voltage transistor. Shallow junctions of less than 2pm are used in common with low-voltage high-frequency devices. High-voltage devices have a specially designed field-plate structure and semi-insulating passivation film. Shallow junction high-voltage structure obtained by computer simulation. Definition of NC, LF, Ls, T and T are shown in Fig. 1. (a)Base-collector junction breakdown characteristics of complementary transistors with the structure shown in Table I. Breakdown voltage of 370V for the NPN transistor and 360V for the PNP transistor are obtained by using collectors doped with a 3~1 0~~c m -~ impurity concentration. (a) Complementary characteristics of NPN and PNP transistors. Excellent complementarity with hFE of more than 50 and low series resistance are obtained, spite of the use of a high-voltage process. (b)fT versus IC characteristics of the PNP and NPN transistors fabricated with the 350V process. (a)Block diagram of the Subscriber Line I-nterface sircuit(SL1C) LSI including battery feed, supervision and 2wire-4wire hybrid functions. (b) Photomicrograph of the SLIC-LSI chip fabricated with the 350V complementary dielectric isolation technique. 1 2 18.8 IEDM 82 -193
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