The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction Branch Target Buffer (BTB) and an IEEE compliant binary floating-point [ 1,21. The microprocessor operates a t 6OOMHz at the fast end of the process distribution, although the system is shipped at 500MHz in a 10t2 SMP configuration. Measured system performance on the 10 way is 1069 9 3 9 0 MIPS. This microprocessor uses a 0.25pm CMOS process. The chip, shown in Figure 5.2.1, uses 6 levels of metal plus an additional layer of local interconnect and is 14.6x14.7mm2 with 25M transistors (7M logic/l8M array). Power supply is 1.9V. Chip power is 25W a t 500MHz.The G5 microprocessor shown in Figure 5.2.2 is based on the G4 processor with enhancements to performance and functionality [3]. It features two instruction units (IU) with a BTB, two fixed point execution units (FXU), two floating point units (FPU) supporting both hex and IEEE binary floating point operations, a buffer control element unit (BCE) containing the L1 cache, and a register-checkpoint unit (RU) to hold the architected state of the machine as well as compare the results of the two IU/ FXU/FPU to ensure state-of-the-art CPU reliability. The FXU has the same functional units as G4: a 64b binary adder, 64b BLU/AIM, and an 8 digit decimal adder, but is enhanced to execute more complex instructions directly in hardware. Most decimal arithmetic instructions are executed directly in hardware and the remaining are assisted by millicode assist instructions. Also, control instructions which modify the processor status word (PSW) are executed in hardware. The L1 cache is now 4 times the size of that ofG4 with a 256kB unified store-through 4-way set associative 2-way interleave design. The TLB is 256x4 way associative. Performance is enhanced in multiprocessor configurations by a quiescing mechanism for invalidating page table entries allowing processors to continue execution up to the next translation. A self-generated clock (SGC) system controls both chip clocking / PLL distribution and self test mode during LBIST.The processor includes several design features which improve reliability and availability such as mirrored execution units and instruction units, dynamic CP sparing and a writeable control store. The mirrored units both operate on the same instructions with results compared by the RU. If an error is detected, all processor arrays are cleared, every critical latch is reset, a shadow register copy of the microarchitected state is reloaded from the RU checkpoint copy, and the processor starts instruction fetchlexecution again. If the processor recovery fails, indicating a hard fault rather than a soft error, dynamic CP sparing is used. This involves unloading the state of the bad CP, dynamically reconfiguring the system, and loading the state into a good CP. A 32KB writable control store array was added for 64 of the most commonly used instructions executed by millicode. Millicode implements complex S/390 instructions,...
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