The single event upset (SEU) sensitivity of certain types of linear microcircuils is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SIX7 control have been suggested.
I. INTRODIJCTIONThe history of the single event upset (SEIJ) study of linear integrated circuits (ICs) is relatively short. The first reporting of SETJs in linear ICs took place in 1993 [l]. This can be compared with the substantially longer history of the total ionizing dose (TID) investigation of linear ICs, including those involving electron irradiation [2,3]. I Iowever, the study of SEIJs in linear ICs (which have also hcen called analog S E W hac. gained attention [4, 5 , 6 ] in recent years partly due to the detrimental effects which may resulc from analog SElJs in space home electronics systems. For ex,mple, battery charging circuits, which incorporate a voltage comparator followed by a D-type flip-flop, have tenninatcd the charging process when the comparator is irradiated by heavy ions. Similar systems have been utilized in space to charge batteries with the use of solar panels. In other cases, analog SEI Js may be tolcrated, although they are a nuisance 171. While previous studies of analog SEUs have included test results obtained for varying bias settings [4,5,6], the majority of the test results have been obtaincd with a rclativcly small number of input bias settings. Therefore, a substantial difference in the sensitivity of a tcst device type due to different bias conditions has not been reported. In ordcr to better understand the upset mechanisms and to possibly mitigate the impact of SElJs on the system, we have exposed several types of linear ICs biased in varying conditions to heavy ions. This has extended the scope of SEU observations in linear ICs to include various quiescent input conditions. The current investigation has led to a finding in which SEIJ sensitivity may be reduced by controlling the quiescent input conditions in some types of linear ICs.
TEST DEVICESTest device types include voltage comparators, operational amplifiers, and other linear integrated circuits, all of which incorporate a difference amplifier circuit at the input section.The input section has been shown to bc sensitive to hcavy ions in similar circuits 111. The test device types are shown in Table 1.The LM119 voltage comparator incorporates npn transistors in the difference amplifier sections @1, D2, and D3) and the level shift section (L) as shown in Figure 1. This is designed for high speed applications and it provides a response time of less than 100 nanoseconds. The positive and the negative inputs (+VIN and -VIN) are directly tied to the transistors 01 and Q2, respectively, in the D1 amplifier.LM139 and LM111 voltage comparators incorporate pnp transistors in the front section, where the initial amplification takes place. These devices are of much older design and have a relatively slow time response. The response times for LM139 and LM111 are about 1.3 microseconds and 200 nanoseconds, respectiv...
