Nanomaterials offer an attractive solution to the challenges faced for low‐cost printed electronics, with applications ranging from additively manufactured sensors to wearables. This study reports hysteresis‐free carbon nanotube thin‐film transistor (CNT‐TFTs) fabricated entirely using an aerosol jet printing technique; this includes the printing of all layers: semiconducting CNTs, metallic electrodes, and insulating gate dielectrics. It is shown that, under appropriate printing conditions, the gate dielectric ink can be reliably printed and yield negligible hysteresis and low threshold voltage in CNT‐TFTs. Flexible CNT‐TFTs on Kapton film demonstrate minimal variations in performance for over 1000 cycles of aggressive bending tests. New insights are also gained concerning the role of charge trapping in Si substrate‐supported devices, where exposure to high substrate fields results in irreversible degradation. This work is a critical step forward as it enables a completely additive, maskless method to fully print CNT‐TFTs of direct relevance for the burgeoning areas of flexible/foldable, wearable, and biointegrated electronics.
Single-walled carbon nanotubes (CNTs) printed into thin films have been shown to yield high mobility, thermal conductivity, mechanical flexibility, and chemical stability as semiconducting channels in field-effect, thin-film transistors (TFTs). Printed CNT-TFTs of many varieties have been studied; however, there has been limited effort toward improving overall CNT-TFT performance. In particular, contact resistance plays a dominant role in determining the performance and degree of variability in the TFTs, especially in fully printed devices where the contacts and channel are both printed. In this work, we have systematically investigated the contact resistance and overall performance of fully printed CNT-TFTs employing three different printed contact materials-Ag nanoparticles, Au nanoparticles, and metallic CNTs-each in the following distinct contact geometries: top, bottom, and double. The active channel for each device was printed from the dispersion of high-purity (>99%) semiconducting CNTs, and all printing was carried out using an aerosol jet printer. Hundreds of devices with different channel lengths (from 20 to 500 μm) were fabricated for extracting contact resistance and determining related contact effects. Printed bottom contacts are shown to be advantageous compared to the more common top contacts, regardless of contact material. Further, compared to single (top or bottom) contacts, double contacts offer a significant decrease (>35%) in contact resistance for all types of contact materials, with the metallic CNTs yielding the best overall performance. These findings underscore the impact of printed contact materials and structures when interfacing with CNT thin films, providing key guidance for the further development of printed nanomaterial electronics.
Semiconducting carbon nanotubes (CNTs) printed into thin films offer high electrical performance, significant mechanical stability, and compatibility with lowtemperature processing. Yet, the implementation of lowtemperature printed devices, such as CNT thin-film transistors (CNT-TFTs), has been hindered by relatively high process temperature requirements imposed by other device layersdielectrics and contacts. In this work, we overcome temperature constraints and demonstrate 1D− 2D thin-film transistors (1D−2D TFTs) in a low-temperature (maximum exposure ≤80 °C) full print-in-place process (i.e., no substrate removal from printer throughout the entire process) using an aerosol jet printer. Semiconducting 1D CNT channels are used with a 2D hexagonal boron nitride (h-BN) gate dielectric and traces of silver nanowires as the conductive electrodes, all deposited using the same printer. The aerosol jet-printed 2D h-BN films were realized via proper ink formulation, such as utilizing the binder hydroxypropyl methylcellulose, which suppresses redispersion between adjacent printed layers. In addition to an ON/ OFF current ratio up to 3.5 × 10 5 , channel mobility up to 10.7 cm 2 •V −1 •s −1 , and low gate hysteresis, 1D−2D TFTs exhibit extraordinary mechanical stability under bending due to the nanoscale network structure of each layer, with minimal changes in performance after 1000 bending test cycles at 2.1% strain. It is also confirmed that none of the device layers require high-temperature treatment to realize optimal performance. These findings provide an attractive approach toward a cost-effective, direct-write realization of electronics.
Flexible and stretchable electronics are poised to enable many applications that cannot be realized with traditional, rigid devices. One of the most promising options for low-cost stretchable transistors are printed carbon nanotubes (CNTs). However, a major limiting factor in stretchable CNT devices is the lack of a stable and versatile contact material that forms both the interconnects and contact electrodes. In this work, we introduce the use of eutectic gallium-indium (EGaIn) liquid metal for electrical contacts to printed CNT channels. We analyze thin-film transistors (TFTs) fabricated using two different liquid metal deposition techniques-vacuum-filling polydimethylsiloxane (PDMS) microchannel structures and direct-writing liquid metals on the CNTs. The highest performing CNT-TFT was realized using vacuum-filled microchannel deposition with an in situ annealing temperature of 150 °C. This device exhibited an on/off ratio of more than 10 and on-currents as high as 150 μA/mm-metrics that are on par with other printed CNT-TFTs. Additionally, we observed that at room temperature the contact resistances of the vacuum-filled microchannel structures were 50% lower than those of the direct-write structures, likely due to the poor adhesion between the materials observed during the direct-writing process. The insights gained in this study show that stretchable electronics can be realized using low-cost and solely solution processing techniques. Furthermore, we demonstrate methods that can be used to electrically characterize semiconducting materials as transistors without requiring elevated temperatures or cleanroom processes.
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