This paper presents the design of an n-type bulk-driven MOSFET which is intended to facilitate the scaling of analogue circuitry down to 0.7 V, the minimum supply voltage predicted for the end of bulk CMOS. The bulk-driven MOSFET design will be carried out in two parts using the design rules of a standard 90 nm bulk CMOS technology. First, the impact of gate oxide scaling will be investigated to see how the bulk transconductance behaves as the oxide thickness is varied. Results will indicate that the oxide scaling requirements of a MOSFET can be relaxed by 0.4 nm when the bulk is used as the input terminal rather than the gate. Second, by taking advantage of a larger oxide thickness, it will be shown that a delta-doped profile is capable of improving the intrinsic gain and cut-off frequency of a bulk-driven MOSFET by as much as 429% and 71%, respectively, when compared to a uniformly doped bulk-driven device consistent with the specifications of a 90 nm bulk CMOS process. Overall, the delta-doped bulk-driven MOSFET will exhibit a long-channel bulk-to-gate transconductance ratio equal to 0.51, compared to 0.27 in the uniformly doped device (the gate transconductance was the same in both devices). The new delta-doped design will also increase the bulk-driven-to-gate-driven cut-off frequency ratio to 0.095-0.492 for channel lengths ranging from 80-800 nm, which is a 16-34% improvement over the uniformly doped case. When used in a differential amplifier circuit, the delta-doped bulk-driven MOSFET was found to have a dc voltage gain 185% higher than that of a similar amplifier utilizing uniformly doped devices.
With the advent of system-on-a-chip integration, analog components are being forced to co-exist with their digital counterparts in scaled processes where the supply voltage, V DD , is expected to fall to 0.7 V by 2012 [1]. As a result of this integration, traditional analog topologies suffer from voltage headroom constraints since the threshold voltage, V T , can no longer scale proportionately with V DD due to sub-threshold leakage constraints. In 1996, Blalock described how the bulk terminal of a MOSFET could be used as a device input to enable analog design at very low supply voltages [2]. Using the MOSFET in this way, one could eliminate V T from the signal path allowing for a significant rise in the available voltage headroom. However, this device, called the bulk-driven (BD) MOSFET, suffered from intrinsic gain limitations because it depended upon the transconductance of the bulk, g mb , rather than the gate (g m ). Since Blalock's initial investigation, there has been no effort undertaken to make the BD MOSFET more adaptable to modern processes even though there have been numerous publications of low voltage analog designs incorporating the use of BD MOSFETs in these technologies. Therefore, this paper takes the first step towards creating a BD MOSFET that has been optimized for modern processes by proposing the use of delta doping [3] to improve g mb ; this claim will be verified through 2-D device simulations in ATLAS [4] and the results will be compared against haloimplanted devices which are currently being used in circuits utilizing the BD MOSFET. Furthermore, this paper will investigate the role that quantum mechanical (QM) confinement and gate oxide thickness, t ox , play in the performance of BD MOSFETs. Simulation results show that QM effects do not degrade g mb as aggressively as g m and that the t ox requirements necessary for gate-driven (GD) devices can be relaxed when using the bulk as an input. Figure 1 displays a cross-section of the delta-doped, n-type BD MOSFET simulated in this paper. The device utilized shallow trench isolation (STI) and had a t ox = 1.4 nm, a junction depth, x j = 30 nm, and a background doping level of: 1 x 10 16 cm -3 ; the source/drain regions and their extensions were doped to: 1 x 10 20 cm -3 and 2 x 10 19 cm -3 , respectively. The lightly-doped layer, t epi , had a thickness of 5 nm and a doping concentration of: 1 x 10 15 cm -3 ; it was designed to reduce ionized impurity scattering in the channel. The delta-doped region was 50 nm thick and had a doping level of: 1.75 x 10 18 cm -3 , 3.25 x 10 18 cm -3 and 7.5 x 10 18 cm -3 which yielded V T 's of: 0.3 V, 0.42 V and 0.6 V, respectively. The device simulations used the energy balance transport equations (hcte.el) to model carrier transport and the Bohm quantum potential model (bqp.n) to account for the movement of inversion layer carriers away from the Si/SiO 2 interface [4]; velocity saturation (fldmob) and impact ionization (toyabe) were also included in the simulation [4]. Fig. 1 Cross-section of a delta-doped...
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