Recrystallization of silicon-on-insulator (SOI) films using a line-source electron beam is described. This unique heat source can continuously emit several kilowatts of - 5 keV electrons into a beam 150 mm in length and - 2.5 mm in width, an exposure area which allows processing of 100 mm substrates in a single pass. An attractive aspect of this beam is the ability to control the beam profile, which in turn allows one to influence the thermal gradients present during recrystallization. Using a tightly focussed beam to recrystallize the SOI layer results in a film whose physical properties are generally attributed to films grown with a high thermal gradient at the solidifying liquid-solid interface (highly branched subboundaries with a maximum spacing of - 20 microns and several degrees of angular mismatch.) By reducing the gradient at the growth interface it is possible to achieve unbranched sub-boundaries with over 70 micron spacing and less than 0.5 degrees of out-of-plane tilt misalignment.
Abstract-Characteristics of n-channel MOSFET's fabricated in cold cathode electron-beam-recrystallized silicon-onoxide layers have been examined. Assorted crystallographic defects exist in the recrystallized silicon layer ranging from highly branched subgrain boundaries to widely spaced parallel subgrains and rows of threading dislocations. Some of these MOSFET transistors have characteristics aPfroaching those fabricated in bulk silicon including = 828-cm /V . s electron surface mobilities and 130-m V/ decade inverse subthreshold slopes. However, many of the devices tested exhibited leakage currents up to 10-6 A/11m, resulting in high inverse subthreshold slopes and reduced threshold voltages. Some effects of crystal imperfections on device behavior are discussed.
Latchup free CMOS devices have been fabricated by forming PMOS transistors in a 0.5μm thick laser recrystallized silicon layer. This recrystallized layer is isolated fram the bulk wafer by a lμm thick oxide layer. The NMOS transistors were fabricated both in the bulk wafer in the region which was used as the recrystallization seeds, as well as in the recrystallized silicon layer itself. Ring oscillators fabricated with 3μm channel length using a bi-layer lateral CMOS structure show a naninal delay of 1.7ns/stage. The MOS devices fabricated in the recrystallized silicon show low subthreshold leakage current, and surface electron and hole mobilities of 580cm2/V.s and 210cm2/V.s respectively.
Latchup free lateral CMOS transistors with PMOS devices in the laser recrystallized silicon and the NMOS devices in the bulk silicon were fabricated. One micron thick field oxide isolates the PMOS devices in the recrystallized silicon from the NMOS devices in the bulk wafer. The seed area for recrystallization was used for the fabrication of the NMOS devices. An oxide layer of 0.1um thickness was used to protect the channel region of the NMOS devices during the laser recrystallization. The effect of this channel protect-oxide is discussed and the characteristics of the NMOS devices with and without the channel protect oxide are compared.
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