The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S-parameter measurements in silicon. These S-parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz.
AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 10Gbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 10Gb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF.I.
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