This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological operations, labeling and feature extraction are required to achieve the real-time performance while tracking will be handled in software in an embedded processor. By implementing a complete embedded system, bottlenecks in computational complexity and memory requirements can be identified and addressed. Accordingly, a memory reduction scheme for the video segmentation unit, reducing bandwidth with more than 70%, and a low complexity morphology architecture that only requires memory proportional to the input image width, have been developed. On a system level, it is shown that a labeling unit based on a contour tracing technique does not require unique labels, resulting in more than 50% memory reduction. The hardware accelerators provide the tracking software with image objects properties, i.e. features, thereby decoupling the tracking algorithm from the image stream. A prototype of the embedded system is running in real-time, 25 fps, on a field programmable gate array development board. Furthermore, the system scalability for higher image resolution is evaluated.
Abstract-This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorithm are explored and modifications are made with potential improvements of segmentation results and hardware efficiency. In addition, to achieve real-time performance with high resolution video streams, a dedicated hardware architecture with streamlined dataflow and memory access reduction schemes are developed. The whole system is implemented on a Xilinx field-programmable gate array platform, capable of real-time segmentation with VGA resolution at 25 frames per second. Substantial memory bandwidth reduction of more than 70% is achieved by utilizing pixel locality as well as wordlength reduction. The hardware platform is intended as a real-time testbench, especially for observations of long term effects with different parameter settings.Index Terms-Field-programmable gate array (FPGA), mixture of Gaussian (MoG), video segmentation.
Abstract-Among many of the algorithms for video segmentation, one based on statistical background model [1] was developed with the unique feature of robustness in multi-modal background scenarios. However, with large amount of calculations due to pixel wise processing of each frame, such an algorithm could only achieve a low frame rate far from real-time requirements on computers. In this paper, a hardware accelerator is proposed, with a dedicated architecture aiming to address the computation as well as memory bandwidth demand. The whole system is targeted to an FPGA platform, which is served as a real-time test bench where long term effects caused by fixed point quantization and various parameter settings can be studied. Meanwhile, memory bandwidth as well as memory size are investigated and reduction by up to 60 percent through similarity exploitation for neighboring Gaussian parameters is envisioned. Furthermore, an controller synthesis tool is used to relieve the effort for the manual design of complex control unit, scheduling the operations of the whole system.
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