Devices with tunable resistance are highly sought after for neuromorphic computing. Conventional resistive memories, however, suffer from nonlinear and asymmetric resistance tuning and excessive write noise, degrading artificial neural network (ANN) accelerator performance. Emerging electrochemical random-access memories (ECRAMs) display write linearity, which enables substantially faster ANN training by array programing in parallel. However, state-of-the-art ECRAMs have not yet demonstrated stable and efficient operation at temperatures required for packaged electronic devices (~90°C). Here, we show that (semi)conducting polymers combined with ion gel electrolyte films enable solid-state ECRAMs with stable and nearly temperature-independent operation up to 90°C. These ECRAMs show linear resistance tuning over a >2× dynamic range, 20-nanosecond switching, submicrosecond write-read cycling, low noise, and low-voltage (±1 volt) and low-energy (~80 femtojoules per write) operation combined with excellent endurance (>109 write-read operations at 90°C). Demonstration of these high-performance ECRAMs is a fundamental step toward their implementation in hardware ANNs.

Recently, a significant amount of attention went toward the development of artificial neural networks, as these promise efficient computation for specific tasks that are expensive or even impossible for von Neumann architecture‐based computers. A considerable amount of research is conducted to develop materials in which layered neural networks are easily implemented. Herein, the use of high‐quality semiconducting single‐walled carbon nanotube (s‐SWCNT) inks to fabricate artificial synapses using simple bottom‐gate field‐effect transistors (FETs) is reported. The synapse utilizes the otherwise often dreaded hysteresis, the characteristic of the device structure, and the materials used therein. This hysteresis spans several orders of magnitude. The SWCNT synaptic transistor exhibits a clear spike‐time‐dependent plasticity (STDP), indicating the ability to achieve learning, following a mechanism similar to biological systems: asymmetric anti‐Hebbian learning. The very well‐defined STDP shape, together with the use of a simple pulse shape to obtain it, has not been reported previously for synaptic transistors. This represents a crucial step for further development of actual hardware implementation of artificial synapses in a more extensive, layered network. Interestingly, the time response of the device is very similar to the one of biological synapse, opening opportunities unavailable to CMOS emulations.