This paper presents a detailed analysis of atomic structure and force variations in metal nanowires under tensile strain. Our work is based on state of the art molecular dynamics simulations and ab initio self-consistent field calculations within the local density approximation, and predicts structural transformations. It is found that yielding and fracture mechanisms depend on the size, atomic arrangement, and temperature. The elongation under uniaxial stress is realized by consecutive quasielastic and yielding stages; the neck develops by the migration of atoms, but mainly by the sequential implementation of a new layer with a smaller cross section at certain ranges of uniaxial strain. This causes an abrupt decrease of the tensile force. Owing to the excessive strain at the neck, the original structure and atomic registry are modified; atoms show a tendency to rearrange in closed-packed structures. In certain circumstances, a bundle of atomic chains or a single atomic chain forms as a result of transition from the hollow site to the top site registry shortly before the break. The wire is represented by a linear combination of atomic pseudopotentials and the current is calculated to investigate the correlation between conductance variations and atomic rearrangements of the wire during the stretch. The origin of the observed ''giant'' yield strength is explained by using results of the present simulations and ab initio calculations of the total energy and Young's modulus for an infinite atomic chain.

No abstract

No abstract

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.

Electronic transport properties of Au nano-structure are investigated using both experimental and theoretical analysis. Experimentally, stable Au nanowires were created using mechanically controllable break junction in air, and simultaneous current-voltage (I-V) and differential conductance δI/δV data were measured. The atomic device scale structures are mechanically very stable up to bias voltage V b ∼ 0.6V and have a life time of a few minutes. Facilitated by a shape function data analysis technique which finger-prints electronic properties of the atomic device, our data show clearly differential conductance fluctuations with an amplitude > 1% at room temperature, and a nonlinear I-V characteristics. To understand the transport features of these atomic scale conductors, we carried out ab initio calculations on various Au atomic wires. The theoretical results demonstrate that transport properties of these systems crucially depend on the electronic properties of the scattering region, the leads, and most importantly the interaction of the scattering region with the leads. For ideal, clean Au contacts, the theoretical results indicate a linear I-V behavior for bias voltage V b < 0.5V . When sulfur impurities exist at the contact junction, nonlinear I-V curves emerge due to a tunnelling barrier established in the presence of the S atom. The most striking observation is that even a single S atom can cause a qualitative change of the I-V curve from linear to nonlinear. A quantitatively favorable comparison between experimental data and theoretical results is obtained. We also report other results concerning quantum transport through Au atomic contacts.

. Performance analysis and optimization of high density tree-based 3d multilevel FPGA. Abstract. A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development of a Tree-based multilevel interconnect network is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to redistribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers discussed. The impact of of Through Silicon Vias and performance improvement on 3D Tree-based FPGA analyzed and also an optimized physical design technology leveraging on TSV, Thermal-TSV (TTSV), and thermal analysis are presented. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and a performance improvement of 53% recorded in our place and route experiments.

No abstract

No abstract