VMP is an experimental multiprocessor that follows the familiar basic design of multiple processors, each with a cache, connected by a shared bus to global memory. Each processor has a synchronous, virtually addressed, single master connection to its cache, providing very high memory bandwidth. An unusually large cache page size and fast sequential memory copy hardware make it feasible for cache misses to be handled in software, analogously to the handling of virtual memory page faults. Hardware support for cache consistency is limited to a simple state machine that monitors the bus and interrupts the processor when a cache consistency action is required.In this paper, we show how the VMP design provides the high memory bandwidth required by modern highperformance processors with a minimum of hardware complexity and cost. We also describe simple solutions to the consistency problems associated with virtually addressed caches. Simulation results indicate that the design achieves good performance providing data contention is not excessive.
TM-1 is the irst in a family of programmable multimedia processor A m the Trimedia product group of PhilipsSemiconductors. This rogrammable processor has a high pelformance V-&dCPU core with video and audio peripheral units designed to support the popular multimedia applications. TM-I is designed to concurrently process video, audio, graphics, and communication data. The VLIW-CPU core is capable of executing a maximum of twenty seven operations per cycle, and the sustained execution rate is about five operations per cycle for the tuned a plications. The audio unit easily handles dflerent au8o formats including the 16-bit stereo data. The video unit is capable o processing diferent scaling and color space conversion. TM-1 applications YUV and RGB pixel formats with hf orizontal and vertical can ran e from low-cost, stand alone systems such as video iones to programmable, multipurpose plug-in cards &r traditional computers.
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