A novel compact model has been developed, which considers the origin of the short-channel effect (SCE) on the basis of the potential distribution along the channel. Thus an enlargement of the insight into SCE suppression in advanced thin-layer MOSFETs is enabled. The model is extended to include the diffusion region resistance effects caused by the drain-side doping by applying the methodology of the industry-standard high-voltage MOSFET model HiSIM_HV. Usage for studying possible device optimizations revealed that clear improvements in the subthreshold characteristics due to suppression of SCEs can be achieved by slightly increasing the drain-side diffusion resistance. Disadvantageous effects on the device and circuit performances were found to be negligible.INDEX TERMS Short channel transistor, compact modeling, double-gate MOSFET, subthreshold characteristics.
A compact model applicable for both Schottky barrier diode (SBD) and junction barrier Schottky diode (JBS) structures is developed. The SBD model considers the current due to thermionic emission in the metal/semiconductor junction together with the resistance of the lightly doped drift layer. Extension of the SBD model to JBS is accomplished by modeling the distributed resistance induced by the p+ implant developed for minimizing the leakage current at reverse bias. Only the geometrical features of the p+ implant are necessary to model the distributed resistance. Reproduction of 4H-SiC SBD and JBS current-voltage characteristics with the developed compact model are validated against two-dimensional (2D) device-simulation results as well as measurements at different temperatures.
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