The ribbon on sacrificial template (RST) process is a ribbon direct-wafering technology with specific ability for high throughput and thin multicrystalline wafer production, in the range of 60-140 μm. Mechanical and electrical properties of the RST material were investigated. Ball on ring and four-point bending tests showed good fracture stress values up to 260 MPa. The conversion efficiency potential for passivated emitter and rear cells (PERC) made out from the RST material, around 16%, is shown to be limited by defects reducing minority carrier lifetime. The interaction between impurities, such as C and transitions metals, with structural defects such as dislocations, results in highly recombinative areas in RST wafers. A model is proposed which shows that the carbon substrate is an important source of carbon contamination in the silicon melt during the growth of the ribbon. This high C contamination can be accompanied by transition metal contamination and can have an influence on the growth stability and on the generation of structural defects, especially if C accumulates in a boundary layer just above the growth interface. The study of the segregation of Sb indicates that the process conditions are close to the case of the diffusive regime near the solid/liquid interface, with a boundary layer thickness of about 70 μm.

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The interest in FOWLP as new flexible packaging technology platform is continuously increasing. High volume capability is proven for configurations with single die (WLFO), multi-die side-by-side, partially with discrete passives integration (WLMCM and WLSiP), both with single sided single and multiple RDL layers. The next step to achieve higher integration density, e.g. for mobile and IoT applications, is to go in the third dimension (WL3D/WLPoP) with total package thickness below 1mm, targeting 0.8mm and even less in the next development step. High design flexibility, superior performance and small form-factor in x and y, but even more important in z-dimension, are the essential packaging characteristics required for this type of smart system integration. The eWLB based WLFO technology platform of NANIUM promises to deliver all of those requirements. While previous generations of WLFO packages only consisted of one plane of single or multiple RDL layers (frontside RDL at BGA side), recent evolutions enable Package-on-Package (PoP) stacking of discrete passives too large to be embedded in the WLSiP, FlipChip, BGA or even another WLSiP on top of a thin bottom WLSiP, enabled by a second plane of single or multiple RDL layers (backside RDL) connected to the frontside RDL by TPV (thru package vias). This is allowing 3D integration on molded reconstituted round panel, resulting in so called WL3D/WLPoP solutions. For TPV processing and even more important to achieve the required total package thickness, WLSiP round recon panels need to be thinned below a thickness that allows self-supported handling of the panel anymore. Arising bow and warp triggers the demand for a temporary carrier solution to enable high backside processing yields at lowest total package thickness. The main challenge is the very high and non-linear thermal expansion of molded panels that needs to be combined with a temporary carrier solution. In this joint paper a study of different temporary carrier solutions, investigating different temporary bonding adhesive classes as well as carrier wafers with different thermal expansion properties will be discussed. The suitability of the carrier systems along the WLSiP panel backside thin-film RDL processing will be evaluated at identified critical process steps. Technology development test vehicles and first products using the newly developed technology will be presented including first reliability and manufacturability test results.