Controlling the recrystallization is an important way to reach grain size refinement and outstanding strength and toughness on alloy metals. This study sets out the application and investigation of mathematical microstructure modeling of a newly designed bainitic steel for hot forging industrial applications. The macro-scale model was used to observe and predict the austenitic grain size behavior during the controlled forging of a gear. Arrhenius grain growth kinetic and recrystallization model for a new class of bainitic steel was established for the given strain rate ranges and temperatures. This model was calibrated through microscopic analysis and used to simulate the unpublished constants of low alloyed bainitic forging steel DIN 18MnCrSiMo6-4 microstructure module using DEFORM® commercial finite element code. The increased temperature due to the adiabatic effect was investigated by numerical analysis, demonstrating its influence on grain coarsening. Local tensile test and Charpy-V notch were compared at different industrial hot forging temperatures and local plastic strain. Changes in yield strength and ductility have demonstrated the grain size influence on the processing parameters. The employed numerical model was an efficient tool to predict and present an alternative path to develop robust industrial forging using semi-empirical models.
Recent increase of transient fault rates has made processor reliability a major concern. Moreover performance improvements are required for many of today's embedded systems. At the same time software implemented fault detection remains the only option for off-the-shelf processors. Software methods, however, introduce significant performance overheads due to the additional instructions required for the detection. A good observation is that often code segments not susceptible to faults are protected. In this paper we propose a technique for systematic analysis of the bit-flip effects on the program controlflow in order to identify only those locations susceptible to controlflow errors and hence minimize the number of fault detection assertions. We instrument the code with minimal overhead, while maintaining high fault coverage level. Our experiments show that using the result of our bit-flip analysis and limiting the code instrumentation to only the susceptible locations releases 28.9% (on average) of the memory while the level of fault coverage remains the same as with full instrumentation.
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