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Hybrid infrared (IR) focal plane arrays consist of an array of IR photodetectors, bump-bonded to a silicon CMOS readout integrated circuit (ROIC) chip. Design and optimisation of ROIC for quantum dot IR detectors is a multidimensional problem. The major design challenge is to select appropriate readout circuit topology to meet the large dynamic range requirement of quantum dot IR photo-detectors within the area dictated by the matched pixel size. Proposed is an efficient design optimisation for ROIC. The optimisation is based on a proposed decision matrix, which leads to a decision merit for ROIC design. Four main specifications, i.e. charge handling capacity, noise, power dissipation and detector bias voltage variations, have been considered. Various architectures have been compared using circuit design, simulation and implementation. The targeted ROIC specifications for a test chip containing a 4 × 4 array are: 5 Mē charge handling capacity, 30 × 30 µm maximum pixel size, snapshot mode of operation, variable integration time, 5 megapixels/s (Mpps) readout rate and readout noise of 600ē at ambient temperature. Also presented is a design with 5 Mē charge handling capacity, which has not been reported for 180 nm CMOS process earlier.

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