A high performance, compact air cooling technology has been developed. It combines the micro-laminar flow concept with an efficient heat sink design in order to achieve a cooling performance comparable to that of complex water cooled modules. The thermal resistance of the micro-laminar heat sinks was measured to be less than 2 degrees centigrade per watt of power dissipated in a l-squarecentimeter chip at an air flow rate of 2 cubic feet per minute. The required air pressure depends on the desired volumetric efficiency.We have demonstrated the capability to remove in excess of 600 watts from a multi-chip module (25 chips at 25 watts and 16% chipto-substrate coverage) with a quiet 10-watt tubeaxial fan. The volume of the complete module including the plenum and the fan is only about 1 liter. The chips are held to a maximum temperature rise of 55 degrees centigrade above ambient. Even higher cooling performance at greater chip-to-substrate coverage was shown to be possible with larger air movers.
This paper describes the electrical design and evaluation of the Josephson cross-sectional model (CSM) experiment. The experiment served as a test vehicle to verify the operation at liquid-helium temperatures of Josephson circuits integrated in a package environment suitable for highperformance digital applications. The CSM consisted offour circuit chips assembled on two cards in a three-dimensional cardoon-board package. The chips (package) were fabricated in a 2.S-llm (S-Ilm) minimum linewidth Pb-alloy technology. A hierarchy of solder and pluggable connectors was used to attach the parts together and to provide electrical interconnections between parts. A data path which simulated a jump control sequence and a cache access in each machine cycle was successfully operated with cycle times down to 3.7 ns. The CSM incorporated the key components of the logic, power, and package of a prototype Josephson signal processor and demonstrated the feasibility of making such a processor with a suM-ns cycle time.
We have simulated the power fidelity of wirebond and flip chip grid array packages suitable for next generation microprocessors. The dc power droop across the chip from resistive losses and the ac power noise from switching events were studied as a function of the number of package power planes, dielectric constant, the number of chip connections, decoupling capacitors, and their location.Simulation program with integrated circuit emphasis (SPICE) was used to simulate the effects of the package and printed wiring board (PWB) characteristics on the differential power supply noise. We varied the number of package power planes, their dielectric constant, and the use of discrete decoupling capacitors and capacitor location with a goal of finding the best low cost design for effective power delivery to the chip.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.