In this paper we present a new roll-to-roll embossing process allowing the replication of micro patterns with feature sizes down to 0.5 mu m. The embossing process can be run in 'continuous mode' as well as in 'discontinuous mode'. Continuous hot embossing is suitable for the continuous output of micro patterned structures. Discontinuous hot embossing has the advantage that it is not accompanied by waste produced during the initial hot embossing phase. This is because in 'discontinuous mode', embossing does not start before the foil has reached the target temperature. The foil rests between two parallel heating plates and foil movement and embossing starts only after the part of the foil resting between the heating plates has reached a thermal steady state. A new type of embossing master is used which is based on flexible silicon substrates. The embossing pattern with sub-mu m topographic resolution is prepared on silicon wafers by state of the art lithography and dry etching techniques. The wafers are thinned down to a thickness of 40 mu m, which guarantees the mechanical flexibility of the embossing masters. Up to 20 individual chips with a size of 20 x 20 mmA(2) were assembled on a roller. Embossing experiments with COC foils showed a good replication of the silicon master structures in the foil. The maximum depth of the embossed holes was about 70% of the master height
Roll-to-roll (R2R) processing on film substrates has been demonstrated to have the potential for achieving high throughput manufacturing of organic electronic systems at low cost. However, the ever-growing mobile devices market accompanied by the developments in information and communication technologies require high performance systems at very low power operation, sometimes on larger substrates having sizes in the range of a few metres. Organic electronics often fall short of fulfilling the required computing performance and power requirements of most of the common use cases. Hybrid integration of inorganic monocrystalline silicon chips on polymer films is a means to fulfil the aforementioned requirements. In this context, it is opportune to report our recent activities on R2R processing of plastic films for hybrid integration of flexible electronics. Hybrid integration can be performed with conventional, rigid surface mount devices as well as flexible, ultrathin bare silicon chips. The first section of the paper is dedicated to a brief overview of R2R manufacturing of electronic devices with an example of production of radio frequency identification tags as well as to a discussion emphasising the targets for hybrid integration. Then, detailed descriptions about our processes for R2R manufacturing of metal wiring lines on films and hybrid integration are included. Three-dimensional integration of films and a temperature sensor label manufactured using hybrid integration process are also elaborated on. Furthermore, key results from fatigue reliability assessment of R2R metallised wiring lines are reported. Finally, some of the challenges in transferring the R2R processes for hybrid integration on film substrates from research labs to industrial manufacturing are highlighted.
Ultra thin silicon ICs with a remaining thickness of less than 30 µm are investigated with respect to their manufacturing technology and mechanical behavior. Thin wafers which were diced using a standard sawing process reveal low fracture resistance when a bending force is applied to single chips. To eliminate influence of micro-cracks induced by sawing extremely thin wafers, the new concept "Dicing by Thinning" was developed and is explained in the paper. The concept allows manufacturing of 10 - 30 µm thin wafers and includes self-acting die separation during thinning procedure. Best results are achieved when dicing lines between chips are prepared at front side of wafer by dry etching methods. First results of analysing mechanical reliability of thin silicon samples are presented and discussed
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