This paper presents two separate but related topics. The first is the <111> to <100> crystal-orientation effects in plasma trench etching where the ratio of etch rates between the orientations is approximately 1:0.63. The second is a trench-etching model in which the etch rate is proportional only to the ion flux incident on the wafer. This requirement is met at high pressures and in inhibitor-layer-assisted processes. In deep trenches, the ion flux on the surface is reduced as the aspect ratio increases. The only fitting parameter is the ion angular standard deviation which is a function of the number of collisions encountered by an ion while crossing the plasma sheath, as found with Monte Carlo simulations that represent this phenomenon. The simulated results predict both the experimental etch rates at the center of the trench and the general profile; however, differences are apparent at the corners and sidewalls of the trench.

For the first time, a scalable, low power, deep-submicron TITSONOS (Thin-Film Transistor Silicon-Oxide-NitrideOxide-Silicon) memory cell is described with characteristics rivaling those of single crystal devices (>IO6 cycles, -1.6V window after 10 years on cycled cell at 85C) showing the promise of 3D integration and ultrasmall cell footprints. The ability to .vertically stack device layers enables the current memory density record of -200Mbyte/cm2, set by 90nm NAND, to be surpassed.

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