A new BiCMOS variable gain transimpedance amplifier with a large area integrated photodiode for automotive applications is presented. Through careful control of the input pole position and the frequency response of the core amplifier, the bandwidth of the transimpedance amplifier varies from 112 to 300 MHz when its gain changes from 14.2 kV to 400 V. The proposed circuit configuration maintains a high voltage across a common anode photodiode, and its bandwidth in highest gain varies from 121 to 102 MHz over a temperature range of 240 to þ1408C. Simulation results in a 0.6 mm Si BiCMOS technology are given. The amplifier consumes 16 mW from a 3.3 V supply.Introduction: Optical transmission technology is increasingly used in cars as an alternative for copper-based solutions [1]. Optical receivers for automotive communication networks must cope with a high ambient temperature range (240 to þ1258C), be cost-effective and low power. Cost-effectiveness implies usage of an integrated photodiode (PD) with large diameter (430 mm in this Letter) to relax the mechanical alignment accuracy requirement, resulting in a high PD capacitance of 4.8 pF. PDs can be made using the p-substrate as an anode and an n þ contact as a cathode [2]. To ensure a fast PD and minimise its capacitance, its reverse bias must be high. This is challenging at a supply voltage of 3.3 V. Variable gain transimpedance amplifiers (TIAs) are needed to ensure high dynamic range. In [3], a variable gain TIA is realised by splitting the core amplifier into two parallel amplifiers and adding their outputs together in a weighted sum fashion. Variable gain was realised by adjusting the weighting factor. However, owing to the varying open-loop gain it is difficult to control the bandwidth and peaking of the frequency response. In [4][5][6], current switches at the input of the TIA are used to steer part of the photodiode current away from the TIA for high optical input power. However, the voltage drop across the current switches results in low bias voltage across a common anode PD. In [7], a Darlington input stage is combined with MOSFETs used as voltage-controlled resistors to achieve wide dynamic range. However, the Darlington input stage is not suitable for a supply voltage of 3.3 V, and the use of ten MOSFETs to control the gain and frequency response makes the circuit design over a wide temperature range difficult. In this Letter we propose a new circuit that overcomes these disadvantages, and can handle a junction temperature range of 240 to þ1408C.
Presented for the first time, is a novel broadband powerline front-end realised in 0.25 mm SiGe BiCMOS with superior performance. The frequency range of the transmitter (TX) and the direct conversion receiver (RX) exceeds 60 MHz with a very wide dynamic range up to 99.5 dB for the lowest channel bandwidth. The integrated IF filter is tunable from 1 up to 8 MHz. The measured input-referred noise of the TX with low third intermodulation distortion (IMD3) is 2140 and 144.5 dBm/Hz for the RX.Introduction: Broadband over powerline communications employing the electricity distribution network is an alternative approach to provide broadband services to users who are not within the deployment strategy of incumbent operators. Many different powerline communication (PLC) systems are being developed and several proposals are under discussion in the IEEE P1901 working group [1]. Frequency division multiplexing (FDM) is undoubtedly the most straightforward way to achieve coexistence between different PLC systems (even homeplug AV includes the possibility to use FDM for coexistence). Besides realising coexistence, there is a strong demand to exploit higher transmission frequencies, to reduce electromagnetic (EM) radiation and to be more robust against interferers. The proposed patent pending powerline front-end IC solves these issues in combination with a high degree of integration, a very high dynamic range, and provides the highest frequency range reported to date.Conventional PLC front-ends, designed for a time division multiple access (TDMA) scheme (e.g. homeplug), do not use frequency conversion in the analogue front-end [2 -4]. As a consequence, the receiver (RX) and the ADC capture the complete frequency range. This puts very high requirements on the ADC in terms of number of bits and conversion rate. Scaling to higher transmission frequencies would require a proportional increase of the ADC conversion rate (e.g. 300 Msps for a 100 MHz system), which is difficult to achieve at low cost and low power consumption. Moreover, the higher the PLC system bandwidth (BW), the more vulnerable the system becomes to interferers [5].Existing powerline front-ends for FDM systems can be divided in two groups. The first employs a classical heterodyne upconversion architecture [6], requiring filters at high IF which are difficult to integrate on chip with good selectivity and linearity. External filters (e.g. SAW filters) are usually used with fixed BW. The second group uses a number of fixed input bandpass filters, which leaves very little flexibility to select the channel frequency and BW [7,8].Design concept: The proposed powerline front-end architecture is shown in Fig. 1. The transmitter (TX) generates a multicarrier signal with variable BW of 2/4/8/16 MHz in the frequency range from 1.6 to 60 MHz. The transmit section on the chip consists of a sixth-order Sallen-Key Butterworth reconstruction filter and a variable gain amplifier (VGA) with a 1 dB gain step, which is connected to the external line driver. The receiver (RX) section...
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