Parasitic capacitances normally present in CMOS transistors are recognized as detrimental factors in overall Transistor & Circuit performance. In this report results from an investigation of a simple method to reduce Junction Capacitance (CJ) in 0.20 and 0.17pm embedded DRAM technologies are presented. The results shown indicate that of both NFETs and PFETs can be reduced (without significantly affecting other transistor parameters) by about 20%.
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