Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Using memristive properties common for the titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to 7-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of CMOS summing amplifier and two memristive devices to perform analog multiply and accumulate computation, which is a typical bottleneck operation in information processing. A natural way to tackle variations in switching behavior is to utilize active feedback scheme, e.g. applying iterative write and read (test) pulses to converge to certain desired conductive state of the device. Such scheme has been successfully applied to phase change memories to achieve multilevel memory operation [Pap11,Bed09]. A similar idea to use closedloop circuitry has been proposed and theoretically simulated using Spice model for TiO 2 devices [Yi11]. In this paper, we experimentally demonstrate a simple feedback algorithm which takes into account specific memristive behavior of titanium dioxide devices to tune resistance state of the device within 1% relative accuracy within all the dynamic range. We then use our algorithm to demonstrate one of the most important operations in information processing -analog multiply and accumulate (MAC). KeywordsThe Pt/TiO 2 (30nm)/Pt devices have been implemented in "bone-structure" geometry with A more accurate control of the device is possible using sequence of relatively large amplitude write pulses followed by smaller non-disturbing read pulses [Pic09]. Note that for all experiments described below we use voltage-controlled pulses for SET switching also. The main reason is that current-controlled switching (or alternatively the utilization of a compliance transistor) is not compatible for large scale crossbar circuits, even though it could be more natural for SET switching in the context of single devices because it allows avoiding overshooting and overheating. In particular, the measurement is composed of two different sequences of pulses: (i) the read pulses of -200 mV and 1 ms width are used to probe the state of the device which is represented by the resistance or by current measured at -200 mV) and (ii) the write pulses which are used to change the state of the memristive device, whether by changing the pulse width and/or the pulse amplitude. The two pulses (read and write) are alternated at a frequency of 0.5 Hz to prevent the accumulative Joule heating effect from single write pulses. highlights that the switching dynamics is exponential with voltage for SET switching and roughly f...

Oxide-based resistive switching devices are promising candidates for new memory and computing technologies. Poor understanding of the defect-based mechanisms that give rise to resistive switching is a major impediment for engineering reliable and reproducible devices. Here we identify an unintentional interface layer as the origin of resistive switching in Pt/Nb:SrTiO3 junctions. We clarify the microscopic mechanisms by which the interface layer controls the resistive switching. We show that appropriate interface processing can eliminate this contribution. These findings are an important step towards engineering more reliable resistive switching devices.

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