Both modern multi- and intermodal supply chains pose a significant challenge to control and maintain while offering numerous optimization potential. Digital Twins have been proposed to improve supply chains. However, as of today, they are only used for certain parts of the entire supply chain. This paper presents an initial framework for a holistic Digital Supply Chain Twin (DSCT) capable of including an entire multimodal supply chain. Such a DSCT promises to enable several improvements all across the supply chain while also be capable of simulating and evaluate several different scenarios for the supply chain. Therefore, the DSCT will not only be able to optimize multi- and intermodal supply chains but also makes them potentially more robust by identifying possible issues early on. This paper discusses the major requirements that such a DSCT must fulfil to be useful and how several information technologies that matured in recent years or are about the mature are the key enablers to fulfil these requirements. Finally, a suggested high-level architecture for such a DSCT is presented as a first step towards the realization of a DSCT, as presented in this work
One of the main challenges for parallel architectures is the increasing complexity of the memory hierarchy, which consists of several levels of private and shared caches, as well as interconnections between separate memories in NUMA machines. To make full use of this hierarchy, it is necessary to improve the locality of memory accesses by reducing accesses to remote caches and memories, and using local ones instead. Two techniques can be used to increase the memory access locality: executing threads and processes that access shared data close to each other in the memory hierarchy (thread affinity), and placing the memory pages they access on the NUMA node they are executing on (data affinity). Most related work in this area focuses on either thread or data affinity, but not both, which limits the improvements. Other mechanisms require expensive operations, such as memory access traces or binary analysis, require changes to hardware or work only on specific parallel APIs.In this paper, we introduce kMAF, a mechanism that automatically manages thread and data affinity on the kernel level. The memory access behavior of the running application is determined during its execution by analyzing its page faults. This information is used by kMAF to migrate threads and memory pages, such that the overall memory access locality is optimized. Extensive evaluation with 27 benchmarks from 4 benchmark suites shows substantial performance improvements, with results close to an oracle mechanism. Execution time was reduced by up to 35.7% (13.8% on average), while energy efficiency was improved by up to 34.6% (9.3% on average).
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