This work Upsampling Constructing the bilateral grid Mapping the problem to the grid Lowresolution flow estimation Hardwarefriendly bilateral solving Mapping the result back Speedup over prior work: CPU 4×, GPU 32×, FPGA 50× High-quality flow field (a) (b) (c) (d) (e) Figure 1: Our bilateral solver produces smooth, edge-aware ow elds. Given an input pair of images (a), a low-resolution ow is estimated (b), upsampled to a noisy high-resolution ow (c), and processed with the bilateral solver (d) to produce an edge-aware smoothed ow (e). Our algorithm for bilateral solving is better-suited for hardware acceleration and results in speedups of up to 50× over prior work [2, 3].
Abstract-Cameras are the defacto sensor. The growing demand for real-time and low-power computer vision, coupled with trends towards high-efficiency heterogeneous systems, has given rise to a wide range of image processing acceleration techniques at the camera node and in the cloud. In this paper, we characterize two novel camera systems that use acceleration techniques to push the extremes of energy and performance scaling, and explore the computation-communication tradeoffs in their design. The first case study targets a camera system designed to detect and authenticate individual faces, running solely on energy harvested from RFID readers. We design a multi-accelerator SoC design operating in the sub-mW range, and evaluate it with real-world workloads to show performance and energy efficiency improvements over a general purpose microprocessor. The second camera system supports a 16-camera rig processing over 32 Gb/s of data to produce real-time 3D-360• virtual reality video. We design a multi-FPGA processing pipeline that outperforms CPU and GPU configurations by up to 10× in computation time, producing panoramic stereo video directly from the camera rig at 30 frames per second. We find that an early data reduction step, either before complex processing or offloading, is the most critical optimization for in-camera systems.
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