This paper presents an investigation work about the bond wire electrical performances, with the aim of designing an integrated time base using the bond wire inductance. Our work was focused on the characterization of single and double gold bond wire, and multi bond wire length for the frequency range from 500 MHz to 5 GHz. A lumped П-model is used for the modeling and the electrical parameters are extracted thanks to the measured S-parameters. A de-embedding procedure is performed to characterize the bond wire. Finally, a structure is proposed to employ the bond wire into an integrated time base.
This paper presents a simple architecture for clock-fault detection in high-speed applications. The overall principle consists in converting a possible error of time to a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected whereas a low voltage level implies a clock error. This detection system is intended for all System-on-Chip such as microcontrollers which use external clock from 4 MHz to 50 MHz. The proposed circuit is realized in CMOS 40 nm process technology. Simulation results prove the suitability of the structure and its integration on silicon is strongly considered by clock error detection in integrated circuits.
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