a b s t r a c tAccurate electrical models are needed to support the design of modern microelectrode arrays. The point-contact model is presented thoroughly, and an area-contact model is analytically derived in order to model the electrical characteristics of the cell-electrode interface at subcellular resolution. An optimum electrode diameter for recording the electrical activity of neurons is analytically determined at 8 mm, with a cell diameter of 10 mm and a typical load capacitance of 10 pF. Finally, three-dimensional tip electrodes are characterized using the area-contact model. An improvement of the electrical coupling up to 20 dB is observed for small electrodes, in simulation.

A new biologically-inspired vision sensor made of one hundred "eyes" is presented, which is suitable for real-time acquisition and processing of 3-D image sequences. This device, named the Panoptic camera, consists of a layered arrangement of approximately 100 classical CMOS imagers, distributed over a hemisphere of 13cm in diameter. The Panoptic camera is a polydioptric system where all imagers have their own vision of the world, each with a distinct focal point, which is a specific feature of the Panoptic system. This enables 3-D information recording such as omnidirectional stereoscopy or depth estimation, applying specific signal processing. The algorithms dictating the image reconstruction of an omnidirectional observer located at any point inside the hemisphere are presented. A hardware architecture which has the capability of handling these algorithms, and the flexibility to support additional image processing in real time, has been developed as a two-layer system based on FPGAs. The detail of the hardware architecture, its internal blocks, the mapping of the algorithms onto the latter elements, and the device calibration procedure are presented, along with imaging results.

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a 3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 V and the power consumption is 7.92 W from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 m 256 m in 0.18-m complementary metal-oxide semiconductor technology.Index Terms-Crosstalk, low-noise neural amplifier, noise efficiency factor, nonlinearity, partial OTA sharing technique.

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 [Formula: see text]m CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 [Formula: see text]W of power within an effective area of 250 [Formula: see text]m × 250 [Formula: see text]m per channel.

We present a CMOS imager with built-in capability to perform Compressed Sensing coding by Random Convolution. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to complete the acquisition model. The feasibility of the imager and its robustness under noise and non-linearities have been confirmed by computer simulations, as well as the reconstruction tools supporting the Compressed Sensing theory.

This paper presents a novel approach to acquire multichannel wireless intracranial neural data based on a compressive sensing scheme. The designed circuits are extremely compact and low-power which confirms the relevance of the proposed approach for multichannel high-density neural interfaces. The proposed compression model enables the acquisition system to record from a large number of channels by reducing the transmission power per channel. Our main contributions are the twofold. First, a CMOS compressive sensing system to realize multichannel intracranial neural recording is described. Second, we explain a joint sparse decoding algorithm to recover the multichannel neural data. The idea has been implemented at system as well as circuit levels. The simulation results reveal that the multichannel intracranial neural data can be acquired by compression ratios as high as four.

Abstract-This paper addresses the functional robustness and fault-tolerance capability of very-deep submicron CMOS and single-electron transistor (SET) circuits. A set of guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. Empirical results based on SPICE simulations show that the proposed design method improves fault immunity at transistor level. Graceful degradation of circuit performance allows recovery of information, where classical circuits would fail. Fault-tolerance; robust very-deep submicron design; CMOS-SET design

Abstract-A point-contact model is presented, and an areacontact model has been analytically derived in order to model the electrical characteristic of the cell-electrode interface of high-density neuron cultures. The area-contact model is presented as a model more suitable for subcellular multielectrode resolution, which is a requisite for modeling and simulating the electrical behavior of novel high-density microelectrode arrays. Furthermore, when the electrode is aligned and centered with the cell, an optimum electrode diameter for recording the electrical activity of neural cells can be analytically derived, which is between 7-8 µm with a typical load capacitance of 10 pF.