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Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV).The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p-silicon and is a function of the distance to the TSV. In addition, the TSV induced stress acts on the barrier layer, the landing pad, the interconnects, and the dielectrics. The interactions with defects may lead to crack nucleation and growth, and compromise the structure reliability. Furthermore, the material choice that reduces silicon stress for less impact on performance may increase stresses in other regions where reliability is of concern. This paper studies these effects and their dependence on various integration configurations.

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