A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a pln junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping.
We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (V T =0.33V), low equivalent oxide thickness (EOT=0.91nm) (T inv =1.3nm) and 83% SiO 2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET V T tuning 2) HfO 2 :SiO 2 alloy ratio with 10% SiO 2 suppressing crystallization up to 1070°C, 3) interlayer SiO 2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI tradeoff, while matching the V T of a SiO 2 /n-PolySi control.
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