This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3-D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxidesemiconductor (MOS) varactor capacitance. The results agree well with 2-D quasi-static simulations and 3-D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3-D integrated system. Index Terms-3D IC, crosstalk, metal-insular-semiconductor (MIS) transmission line, through silicon via (TSV). I. INTRODUCTION P OWER delivery and dissipation are the primary limiters of performance and integration in CMOS scaling [1]-[3]. Conventional 2-D integration technologies are also limited in terms of bandwidth. As an example, the only way to achieve >1 TB/s memory bandwidth between a CPU and memory module has been identified as memory on logic using 3-D integration in [4]. Hence, 3-D IC integration is a necessary path for further power reduction and improved bandwidth in electronic systems. Even though other approaches have been studied in the past toward a 3-D computer [5], the 3-D IC integration technology and silicon interposers at the present rely on through silicon vias (TSVs) for vertical interconnections. The improvement in power and bandwidth by adapting a 3-D integration methodology, therefore, depends on the electrical properties of TSVs. At the present, 3-D integration technology is rapidly evolving with different configurations being investigated. One major classification can be made in terms of the choice of bonding sides of the dies consisting of face-to-face, back-to-back, and face-toback bonding. Another major classification can be made in terms of the TSV process order consisting of via-first, via-middle, and via-last approaches. An example is shown in Fig. 1, which corresponds to a via-last, face-to-back configuration. Various TSV Manuscript

No abstract

SUMMARYIn this paper, equivalent circuit representations for frequency-dependent RLGC (resistance, inductance, conductance and capacitance) parameters of interconnects are presented. Several novel approaches are proposed and compared with each other to model the frequency-dependent behaviour of interconnects due to substrate and conductor losses. The network representations are obtained by network synthesis of suitable non-rational immittances based on analytical methods. Due to the closed-form description of the circuit elements, which consist of positive-valued resistors, inductors, and capacitors, the proposed models can be conveniently implemented in generic circuit simulators.

Multilayered packages and boards, such as high performance server boards, contain thousands of signal lines, which have to be routed on and through several layers with power/ground planes in between. There can be noise coupling not only in the transversal direction through the power/ground planes in such a structure, but also vertically from one plane pair to another through the apertures and via holes. In addition, the continuous increase in power demand along with reduced Vdd values results in significant current requirement for the future chips. Hence, the parasitic effects of the power distribution system become increasingly more critical regarding the signal integrity and electromagnetic interference properties of cost-effective high-performance designs. We present a multilayer finite-difference method (M-FDM), which is capable of characterizing such noise coupling mechanisms. This method allows to consider realistic structures, which would be prohibitive to simulate using fullwave simulators.

No abstract