A reconfigurable platform for sensor networks is presented. This platform has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch. The node includes an FPGA which is the core of the reconfiguration capabilities of the node. Several hardware interfaces for sensor standar protocols like I2C or PWM have been developed and implemented in the FPGA. Remote reconfiguration is an important feature and sensor networks can take advantage of it in order to improve the global performance.
El acceso a la versión del editor puede requerir la suscripción del recurso Access to the published version may require subscription A comparison of simulation and hardware-in-the-loop alternatives for digital control of power converters Alberto Sanchez, Angel de Castro, Member, IEEE, and Javier Garrido, Member, IEEE Abstract-Debugging digital controllers for power converters can be a problem because there are both digital and analog components. This paper focuses on debugging digital controllers to be implemented in FPGAs or ASICs, which are designed in hardware description languages. Four methods are proposed and described. All of them allow simulation, and two methods also allow emulation -synthesizing the model of the converter to run the complete closed loop system in actual hardware. The first method consists in using a mixed analog and digital simulator. This is the easiest alternative for the designer, but simulation time can be a problem, specially for long simulations like those necessary in power factor correction or when the controller is very complex, for example with embedded processors. The alternative is to use pure digital models, generating a digital model of the power converter. Three methods are proposed: real type, float type and fixed point models (in the latter case including hand-coded and automatic-coded descriptions). Float and fixed point models are synthesizable, so emulation is possible, achieving speedups over 20,000. The results obtained with each method are presented, highlighting the advantages and disadvantages of each one. Apart from that, an analysis of the necessary resolution in the variables is presented, being the main conclusion that 32-bit floating point is not enough for medium and high switching frequencies.
This work proposes a new DPWM architecture that takes advantage of FPGA's advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.
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